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Features
* Single-chip Synthesizer + Effects, Features include
- High-quality Wavetable Synthesis, Serial MIDI In & Out, MPU-401 (UART) - Effects: Reverb + Chorus, on MIDI and/or Audio In - Up to 64-voice Polyphony - Surround on Two or Four Speakers with Intensity/Delay Control - Four-band Parametric Equalizer - Audio-in Processing through Reverb, Chorus, Equalizer, Surround Low Chip Count in Applications - ATSAM2133B Synthesizer, ROM/Flash, DAC - Built-in (32K x 16) Effects RAM Low-power - 40 mA Typical Operating Current, <1 A Power-down - 2.5V and 3.3V Supply - Built-in Power Switch 16-bit Samples, 44.1 KHz Sampling Rate, 24 dB Digital Filter per Voice Available Wavetable Firmwares and Sample Sets - CleanWave8(R) Low-cost General MIDI 1-MB Firmware + Sample Set - CleanWave32(R) Top-quality 4-MB Firmware + Sample Set - Other Sample Sets Available under special conditions Built-in ROM Debugger, Flash Programmer through Dedicated Pins - Fast Product-to-market Small Footprint - 12 x 12 mm, 0.4 mm Pitch, 100-lead TQFP Package - 10 x 10 mm, 0.8 mm Pitch 100-ball CBGA Package Typical Applications - Portable Telephones - Computer Karaoke, Portable Karaoke Systems - Keyboards, Portable Keyboard Instruments
* *
Sound Synthesis ATSAM2133B Low-power Synthesizer with Effects and Built-in RAM
* *
* * *
Description
The ATSAM2133B is a low-cost derivative of the ATSAM97xx series. It retains the same high-quality synthesis with up to 64-voice polyphony. The ATSAM2133B maximum wavetable memory is 16 MB and the parallel communication is via a standard MPU-401. The integrated 32K x 16 RAM allows for high-quality effects without additional components. The highly integrated architecture of the ATSAM2133B combines a specialized highperformance RISC-based digital signal processor (Synthesis/DSP) and a general-purpose 16-bit CISC-based control processor on a single chip. An on-chip memory management unit (MMU) allows the synthesis/DSP and the control processor to share external ROM and/or RAM memory devices. An intelligent peripheral I/O interface function handles other I/O interfaces, such as the MPU port, the on-chip MIDI UART, and the Codec control interface, with minimum intervention from the control processor.
Rev. 2694A-DRMSD-05/03
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Typical Applications
Figure 1. Portable Telephone
ATSAM2133B
CleanWave ROM
DAC or Codec
General MIDI-compliant Wavetable Synthesis Parallel or Serial Interface Reverb + Chorus Surround Four-band Parametric Equalizer Audio-in Effects (Codec required)
Figure 2. Low-cost Karaoke, Hand-held Karaoke
ATSAM2133B
CleanWave ROM
Codec
General MIDI-compliant Synthesis Sound Extensions (CleanWave 32) Compatible Reverb + Chorus MIDI Serial or 8-bit Parallel Interface Surround Effect Four-channel Surround (Requires Extra DAC) Four-band Equalizer Microphone Echo
Figure 3. Low-cost Keyboard Instrument
ATSAM2133B
CleanWave ROM
DAC
General MIDI-compliant Synthesis Sound Extensions (CleanWave 32) Compatible Reverb + Chorus MIDI Serial or 8-bit Parallel Interface Surround Effect Four-band Parametric Equalizer
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General Description
Block Diagram
Synthesis/DSP
ATSAM2133B
P16 Processor 16-bit CISC Processor Core includes 256 x 16 Data RAM
64-slot RISC DSP Core includes 512 x 32 Alg RAM 128 x 28 MA1 RAM 256 x 28 MA2 RAM 256 x 28 MB RAM 256 x 16 MX RAM 256 x 12 MY RAM 64 x 13 ML RAM
Codec + DAC
32K x 16 RAM
MMU Memory Management Unit I/O Functions includes Control/Status MIDI UART Timers Codec Data I/F Host I/F FIFO ROM Debug/Flash Prog
ROM or Flash
MIDI MPU Debug/Flash Prog
Synthesis/DSP Engine
The synthesis/DSP engine operates on a frame timing basis with the frame subdivided into 64 process slots. Each process is, in turn, divided into 16 micro-instructions known as algorithms. Up to 32 synthesis/DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be programmed for a number of audio signal generation/processing applications. The synthesis/DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for each voice. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. A typical application will use half the capacity of the synthesis/DSP engine for synthesis, thus providing state-of-the-art 32-voice wavetable polyphony. The remaining processing power will be used for typical functions such as reverberation, chorus, audio-in processing, surround effect, equalizer, etc. Frequently-accessed synthesis/DSP parameter data are stored in five banks of on-chip RAM memory. Sample data or delay lines, which are accessed relatively infrequently, are stored in external ROM or internal 32K x 16 RAM memory. The combination of localized micro-program memory and localized parameter data allows micro-instructions to execute in 20 ns (50 MIPS). Separate buses from each of the on-chip parameter RAM memory banks allow highly parallel data movement to increase the effectiveness of each micro-instruction. With this architecture, a single micro-instruction can accomplish up to six simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 300 million operations per second (MOPS).
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P16 Control Processor and I/O Functions
The P16 control processor is a general-purpose 16-bit CISC processor core that runs from external memory. It includes 256 words of local RAM data memory. The P16 control processor writes to the parameter RAM blocks within the synthesis/DSP core in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART or from the MPU-401 interface and then controls the Synthesis/DSP by writing into the parameter RAM banks in the DSP core. Slowly-changing synthesis functions, such as LFOs, are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables. The P16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the MPU401 interface through specialized intelligent peripheral I/O logic. This I/O logic automates many of the system I/O transfers to minimize the amount of overhead processing required from the P16. The MPU-401 interface is implemented using one address line (A0), a chip select signal, read and write strobes from the host and an 8-bit data bus (D0 - D7). Karaoke and keyboard applications can take advantage of the 8-bit MPU-401 interface to communicate with the ATSAM2133B at high speed, with the MIDI IN and MIDI OUT signals remaining available.
Memory Management Unit (MMU)
The Memory Management Unit (MMU) block allows external ROM/Flash and/or internal 32K x 16 RAM memory resources to be shared between the synthesis/DSP and the P16 control processor. This allows a single device (i.e., internal RAM) to serve as delay lines for the synthesis/DSP and as data memory for the P16 control processor.
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Pin Description
100-lead TQFP Package
Table 1. Pin by Function - 100-lead TQFP Package
Pin Name GND Pin Number 10, 16, 31, 36, 45, 56, 68, 76, 80, 84, 96 11, 37, 83, 86, 87 17, 30, 44, 57, 69, 97 77 78 6-9, 12-15 2 4 3 5 Type PWR Function Power ground - all GND pins should be returned to digital ground.
VC2
PWR
Core power +2.5V 10%. All VC2 pins should be returned to +2.5V. If the built-in power switch is used for minimum power down consumption, then all these pins should be connected to PWROUT, the output of the built-in power switch. Periphery power +2.25V to 3.7V. All VC3 pins should be returned to nominal +3.3V. VC3 should not be lower than VC2. Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this pin must be connected to nominal 2.5V. Power switch output. Use this pin to supply 2.5V core power by connecting it to all VC2 pins. 8-bit data bus to host processor. Information on these pins is parallel MIDI (MPU-401 type applications) Chip select from host, active low. Write from host, active low. Read from host, active low. Selects MPU-401 internal registers: 0 = data registers (read/write) 1 = status register (read) control register (write) Tri-state output pin, active high. Master reset input, active low. Crystal connection. Crystal frequency should be Fs*256 (typ 11.2896 MHz). Crystal frequency is internally multiplied by 4 to provide the IC master clock. An external 11.2896 MHz clock can also be used on X1 (2.5VPP max through 47pF capacitor). X2 cannot be used to drive external ICs; use CKOUT instead. Buffered X2 output, can be used to drive external DAC master clock (256 * Fs) Two stereo serial audio data output (4 audio channels). Each output holds 64 bits (2 x 32) of serial data per frame. Audio data has up to 20 bits precision. DABD0 can hold additional control data (mute, A/D gain, D/A gain, etc.) Audio data bit clock, provides timing to DABD0 - 1, DAAD. Audio data word select. The timing of WSBD can be selected to be I2S or Japanese compatible. Stereo serial audio data input. General-purpose programmable I/O pins. Debug clock. Should be connected to VC3 under normal operation. If DBCLK is found low just after RESET, then the internal ROM debugger/flash programmer is started. Debug data. Allows serial communication for debug/flash programming. Debug acknowledge. Toggled each time a bit is received/sent on DBDATA.
VC3 PWRIN PWROUT D0 - D7 CS WR RD A0
PWR PWR PWR I/O IN IN IN IN
IRQ RESET X1, X2
1 22 81, 82
TSOUT IN -
CKOUT DABD0 -1
88 93, 92
OUT OUT
CLBD WSBD DAAD P0 - P3 DBCLK DBDATA DBACK
94 95 98 18 - 21 90 91 89
OUT OUT IN I/O IN I/O OUT
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Table 1. Pin by Function - 100-lead TQFP Package (Continued)
Pin Name MIDI IN MIDI OUT WA0 - 22 Pin Number 100 99 24 - 29, 32 - 35, 38 - 43, 46 - 52 58 - 67, 70 - 75 53 55 54 85 23 79 Type IN OUT OUT Function MIDI IN input MIDI OUT output External memory address (ROM/Flash). Up to 16 MB.
WD0 - 15 WCS WWE WOE LFT TEST PDWN
I/O OUT OUT OUT ANA IN IN
External ROM/FLASH data External ROM/FLASH chip select, active low. External FLASH write enable, active low. External ROM/FLASH output enable, active low. PLL low-pass filter, should be connected to an external RC network. Test pin, should be returned to GND. Power down, active low, all outputs except WCS, WWE, WOE are set to logic 0, the PLL and crystal oscillator are stopped. If the power switch feature is used, then 2.5V supply voltage is removed from the core. To exit from power down, PDWN must be set to VC2, then RESET applied. When unused, this pin must be connected to VC2.
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Table 2. Pinout by Pin Number - 100-lead TQFP Package
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal Name IRQ CS RD WR A0 D0 D1 D2 D3 GND VC2 D4 D5 D6 D7 GND VC3 P0 P1 P2 P3 RESET TEST WA0 WA1 Pin Number 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name WA2 WA3 WA4 WA5 VC3 GND WA6 WA7 WA8 WA9 GND VC2 WA10 WA11 WA12 WA13 WA14 WA15 VC3 GND WA16 WA17 WA18 WA19 WA20 Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name WA21 WA22 WCS WOE WWE GND VC3 WD0 WD1 WD2 WD3 WD4 WD5 WD6 WD7 WD8 WD9 GND VC3 WD10 WD11 WD12 WD13 WD14 WD15 Pin Number 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name GND PWRIN PWROUT PDWN GND X1 X2 VC2 GND LFT VC2 VC2 CKOUT DBACK DBCLK DBDATA DABD1 DABD0 CLBD WSBD GND VC3 DAAD MIDI OUT MIDI IN
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100-ball LFBGA Package
Table 3. Pin by Function - 100-ball LFBGA Package
Pin Name GND Pin Number A3, A9, C7, D5, D10, E1, F7, G4, G5, J5, J8 B6, C5, C6, E2, H6 Type PWR Function Power ground - all GND pins should be returned to digital ground
VC2
PWR
Core power +2.5V 10%. All VC2 pins should be returned to +2.5V. If the built-in power switch is used for minimum power-down consumption, then all these pins should be connected to PWROUT, the output of the built-in power switch. Periphery power 2.25V to 3.7V. All VC3 pins should be returned to nominal +3.3V. VC3 should be lower than VC2. Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this pin must be connected to nominal 2.5V Power switch output. Use this pin to supply 2.5V core power by connecting it to all VC2 pins. 8-bit data bus to host processor. Information on these pins is parallel MIDI (MPU-401 type applications). Chip select from host, active low. Write from host, active low. Read from host, active low. Selects MPU-401 internal registers: 0: data registers (read/write) 1: status register (read) control register (write) Tri-state output pin, active high. Master reset input, active low. Crystal connection. Crystal frequency should be Fs * 256 (typ 11.2896 MHz). Crystal frequency is internally multiplied by 4 to provide the IC master clock. An external 11.2896 MHz clock can also be used on X1 (2.5VPP max through 47 pF capacitor). X2 cannot be used to drive external ICs; use CKOUT instead. Buffered X2 output. Can be used to drive external DAC master clock (256 * Fs) Two stereo serial audio data output (4 audio channels). Each output holds 64 bits (2 x 32) of serial data per frame. Audio data precise up to 20 bits. DABD0 can hold additional control data (mute, A/D gain, D/A gain, etc.) Audio data bit clock, provides timing to DABD0 - 1, DAAD. Audio data word select. The timing of WSBD can be selected to be I2S or Japanese compatible. Stereo serial audio data input. General-purpose programmable I/O pins. Debug clock. Should be connected to VC3 under normal operation. If DBCLK is found low just after RESET, then the internal ROM debugger/flash programmer is started Debug data. Allows serial communication for debug/flash programming Debug ack. Toggled each time a bit is received/sent on DBDATA MIDI IN input MIDI OUT output
VC3 PWRIN PWROUT D0 - D7 CS WR RD A0
C3, D8, G2, G10, H4, H7 A8 B7 E4, D1, E3, F4, F3, F5, F2, F1 C1 C2 D2 D3
PWR PWR PWR I/O IN IN IN IN
IRQ RESET X1, X2
B1 H3 D6, A7
TSOUT IN -
CKOUT DABD0 - 1
E5 A4, B4
OUT OUT
CLBD WSBD DAAD P0 - P3 DBCLK DBDATA DBACK MIDI IN MIDI OUT
C4 B3 A2 G1, G3, H2, H1 A5 D4 B5 A1 B2
OUT OUT IN I/O IN I/O OUT IN OUT
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Table 3. Pin by Function - 100-ball LFBGA Package (Continued)
Pin Name WA0 - 22 Pin Number J2, K1, K2, K3, J4, J3, K4, H5, G6, K5, F6, J6, K6, G7, J7, K7, K8, H8, K9, J9, K10, J10, H10 F8, E7, F10, F9, E8, E6, E9, E10, D7, D9, C9, C10, C8, B10, B9, A10 G9 G8 H9 A6 J1 B8 Type OUT Function External memory address (ROM/FLASH). Up to 16 Mega bytes.
WD0 - 15
I/O
External ROM/FLASH data
WCS WWE WOE LFT TEST PDWN
OUT OUT OUT ANA IN IN
External ROM/FLASH chip select, active low. External FLASH write enable, active low. External ROM/FLASH output enable, active low. PLL low pass filter. Should be connected to an external RC network. Test pin. Should be returned to GND. Power down, active low, all outputs except WCS, WWE, WOE are set to logic 0, the PLL and crystal oscillator are stopped. If the power switch feature is used, then 2.5V supply voltage is removed from the core. To exit from power down, PDWN must be set to VC2, then RESET applied. When unused this pin must be connected to VC2.
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Table 4. Pinout by Pin Number - 100-ball LFBGA Package
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 Signal Name MIDI IN DAAD GND DABD0 DBCLK LFT X2 PWRIN GND WD15 IRQ MIDI OUT WSBD DABD1 DBACK VC2 PWROUT PDWN WD14 WD13 CS WR VC3 CLBD VC2 Pin Number C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 Signal Name VC2 GND WD12 WD10 WD11 D1 RD A0 DBDATA GND X1 WD8 VC3 WD9 GND GND VC2 D2 D0 CKOUT WD5 WD1 WD4 WD6 WD7 Pin Number F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 Signal Name D7 D6 D4 D3 D5 WA10 GND WD0 WD3 WD2 P0 VC3 P1 GND GND WA8 WA13 WWE WCS VC3 P3 P2 RESET VC3 WA7 Pin Number H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 Signal Name VC2 VC3 WA17 WOE WA22 TEST WA0 WA5 WA4 GND WA11 WA14 GND WA19 WA21 WA1 WA2 WA3 WA6 WA9 WA12 WA15 WA16 WA18 WA20
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Absolute Maximum Ratings
Table 5. Absolute Maximum Ratings
Ambient Temperature (Power applied)........... -40C to + 85C Storage Temperature .................................... -65C to + 150C Voltage on Input Pins ................................. -0.5V to VC3 + 0.3V (except X1 and PDWN) Voltage on X1 and PDWN Pins.................. -0.5V to VC2 + 0.3V VC2 Supply Voltage ..............................................-0.5V to + 3V VC3 Supply Voltage ...........................................-0.5V to + 4.5V Maximum IOL per I/O pin................................................. 4 mA Maximum Input Current per Input Pin.............................. 4 mA Maximum Output Current from PWROUT Pin ............. 525 mA (max duration = 1 sec) *NOTICE:
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Table 6. Recommended Operating Conditions
Symbol VC2 VC3 PWRIN IPWROUT tA Parameter Supply voltage Supply voltage Power supply Power switch output current Operating ambient temperature Min 2.25 VC2 2.25 0 Typ 2.5 3.3 2.5 Max 2.75 3.6 2.95 175 70 Unit V V V mA C
DC Characteristics
Table 7. DC Characteristics (tA = 25C, VC2 = 2.5V 10%, VC3 = 3.3V 10%)
Symbol VIL VIH VIL VIH VOL VOH Parameter Low-level input voltage (Except X1, PDWN) High-level input voltage (Except X1, PDWN) Low-level input voltage for X1, PDWN High-level input voltage for X1, PDWN Low-level output voltage IOL = -2mA High-level output voltage IOH = 2mA Power consumption (crystal frequency =11.2896 MHz) Power down supply current (using power switch) Drop down from PWRIN to PWROUT (at IPWROUT = 100 mA) Min -0.3 2.3 -0.3 2 2.9 Typ 90 1 5 0.1 Max 1.0 VC3+0.3 0.6 VC2+0.3 0.4 Unit V V V V V V mW A V
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Timings
All timing conditions: VC2 = 2.5V, VC3 = 3.3V, tA = 25C, all outputs except X2 and LFT load capacitance = 30 pF. All timings refer to tCK, the internal master clock period. The internal master clock frequency is four times the frequency at pin X1. Therefore tCK = tXTAL/4. The sampling rate is given by 1/(tCK x 1024). The maximum crystal frequency/clock frequency at X1 is 12.288 MHz (48 kHz sampling rate).
Crystal Frequency Selection
There is a trade-off between the crystal frequency and the support of widely-available external ROM/Flash components. Table 8 gives information on selecting the best fit for a given application. Table 8. Crystal Frequency Selection Parameters
Sample Rate (KHz) 48 44.1 37.5 31.25 Crystal (MHz) 12.288 11.2896 9.60 8.00 tCK (ns) 20.35 22.14 26.04 31.25 ROM tA (ns) 92 101 120 146 Comments Maximum frequency Recommended for current designs
Using 11.2896 MHz crystal frequency allows the use of widely-available ROMs with 100 ns access time while providing state-of-the-art 44.1 kHz sampling rate.
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PC Host Interface
Figure 4. Host Interface Read Cycle
A0 tAVCS CS
tCSLRDL RD
tPRD
tRDHCSH
tRDLDV D0 - D7
tDRH
Figure 5. Host Interface Write Cycle
tWRCVC A0 tAVCS CS
tCSLWRL RD
tPWR
tWRHCSH
tDWS D0 - D7
tDWH
Table 9. PC Host Interface Timing Parameters
Symbol tAVCS tCSLRDL tRDHCSH tPRD tRDLDV tDRH tCSLRWRL tWRHCSH tPWR tDWS tDWH tWRCYC Parameter Address valid to chip select low Chip select low to RD low RD high to CS high RD pulse width Data out valid from RD Data out hold from RD Chip select low to WR low WR high to CS high WR pulse width Write data setup time Write data hold time Write cycle Min 0 5 5 50 5 5 5 50 10 0 128 Typ Max 20 10 Unit ns ns ns ns ns ns ns ns ns ns ns tck
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External ROM/Flash
Figure 6. ROM/Flash Read Cycle
tRC WCS0 tCSOE WA0 - WA21 tPOE WOE tOE WD0 - WD15 tACE tDE
Table 10. External ROM/Flash Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tDE Parameter Read cycle time Chip select low/address valid to WOE low Output enable pulse width Chip select/address access time Output enable access time Chip select or WOE high to input data Hi-Z Min 5 * tCK 2 * tCK - 5 5 * tCK - 5 3 * tCK - 5 0 Typ 3 * tCK Max 6 * tCK 3 * tCK + 5 2 * tCK - 5 Unit ns ns ns ns ns ns
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Figure 7. External Flash Write Cycle
tWC WCS1 tCSWE WA0 - WA21
WOE tWP WWE tDW WD0 - WD15 tDH
Table 11. External Flash Timing Parameters
Symbol tWC tCSWE tWP tDW tDH Parameter Write cycle time Write enable low from CS or Address or WOE Write pulse width Data out setup time Data out hold time Min 5 * tCK 2 * tCK - 10 4 * tCK - 10 10 Typ 4 * tCK Max 6 * tCK Unit ns ns ns ns ns
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Digital Audio
Figure 8. Digital Audio
tCW WSBD tCW tCLBD
CLBD tSOD DABD0 DABD1 DAAD tSOD
Table 12. Digital Audio Timing Parameters
Symbol tCW tSOD tCLBD Parameter CLBD rising to WSBD change DABD valid prior/after CLBD rising CLBD cycle time Min 8 * tCK - 10 8 * tCK - 10 16 * tCK Typ Max Unit ns ns ns
Figure 9. Digital Audio Frame Format
WSBD (I2S) WSBD (Japanese)
CLBD
DABD0 DABD1 DAAD MSB LSB 16 bits LSB 18 bits LSB 20 bits MSB
Notes:
1. Selection between I2S and Japanese format is a firmware option. 2. DAAD is 16 bits only.
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Reset and Powerdown
During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized. This can take about 20 ms. After the low-to-high transition of RESET, the following occurs: * * Synthesis/DSP enters an idle state P16 program execution starts from address 0100H in ROM space (WCS low)
If PDWN is asserted low, then the crystal oscillator and PLL are stopped. If the power switch is used, then the chip enters a deep power-down sleep mode, as power is removed from the core. To exit power down, PDWN must be asserted high, then RESET applied. Power-down mode is managed by an internal power switch. The equivalent schematic and standard connection is shown on the diagram below. All the VC2 pins must be connected to PWROUT. Figure 10. Schematic
VC2 Source from Power Supply PDWN = L: Power-down Mode (Internal Power Switch Open) PDWN = H: Operating Mode (Internal Power Switch Closed)
PWRIN
PDWN
PWROUT
ATSAM2133B
VC2 VC2 VC2 VC2 VC2 VC2
Note:
High level for PDWN is VC2 = 2.5V 10%.
Figure 11. PDWN Connection
3.3V 3.3V 2.5V
VC3
VC3
PWRIN
VC2
PWROUT 10 kOhm PDWN Control (High level = 3.3V) PDWN
HOST
ATSAM2133B
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Recommended Board Layout
Like all HCMOS high integration ICs, the following simple rules of board layout are mandatory for reliable operation: * GND, VC3, VC2 Distribution and Decouplings All GND, VC3, VC2 pins should be connected. A GND plane is strongly recommended below the ATSAM2133B. The board GND + VC3 distribution should be in grid form. Recommended VC2 decoupling is 0.1 F at each corner of the IC with an additional 10 F decoupling close to the crystal. VC3 requires a single 0.1uF decoupling. * Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-CR and the ATSAM2133B should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from ATSAM2133B. * Buses Parallel layout between D0 - D7 and WA0 - WA21/WD0 - WD15 should be avoided. The D0 - D7 bus is an asynchronous type bus. Even on short distances, it can induce pulses on WA0 - WA21/WD0 - WD15 that can corrupt address and/or data on these buses. A ground plane should be implemented below the D0 - D7 bus, which is connected to the host and to the ATSAM2133B GND. A ground plane should be implemented below the WA0 - WA21/WD0 - WD15 bus, which is connected to the ROM/Flash grounds and to the ATSAM2133B. * Analog Section A specific AGND ground plane should be provided, which is connected to the GND ground by a single trace. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the analog section.
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Recommended Crystal Compensation and LFT Filter
Figure 12. Recommended Crystal Compensation and LFT Filter
81 X1 82 85 C2
1 nF
X1 X2 LFT
R1
470 Ohm
C4
22 pF
C1
22 pF
C3
10 nF
GND
GND
GND
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Mechanical Dimensions
100-lead TQFP Package
Figure 13. Thin Plastic 100-lead Quad Flat Pack (TQFP100)
Table 13. 100-lead TQFP Package Dimensions (in mm)
Parameter A A1 A2 D D1 E E1 L P B 0.13 0.45 Min 1.40 0.05 1.35 Nom 1.50 0.10 1.40 14.00 12.00 14.00 12.00 0.60 0.40 0.18 0.23 0.75 Max 1.60 0.15 1.45
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100-ball LFBGA Package
Figure 14. Low Profile Fine Pitch 100-ball Grid Array (LFBGA)(Bottom View)
Package Marking
Figure 15. Package Marking
FRANCE
SAM2133B-G
YYWW 57542B XXXXXXXXX
Note:
A1 Ball in lower left-hand corner.
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Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
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Regional Headquarters
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Microcontrollers
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ASIC/ASSP/Smart Cards
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Japan
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e-mail
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2694A-DRMSD-05/03 0M

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